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L9951 L9951XP
Rear door actuator driver
Features
Type Outputs(1) OUT1 OUT2 OUT3 OUT4 OUT5 Ron(2) 150 m 200 m 200 m 800 m 800 m IOUT 7.4 A 5A 5A 1.25 A 1.25 A VS
L9951 L9951XP
28 V
PowerSO-36
PowerSSO-36
1. See block diagram. 2. Typical values.
Applications
One half bridge for 7.4 A load (Ron = 150 m) Two half bridges for 5 A load (Ron = 200 m) Two highside drivers for 1.25 A load (Ron = 800 m) Programmable softstart function to drive loads with higher inrush currents (i.e.current > 7.4A, >5A, >1.25A) Very low current consumption in standby mode (IS < 3A, typ. Tj 85C) All outputs short circuit protected Current monitor output for all highside drivers All outputs over temperature protected Open-load diagnostic for all outputs Overload diagnostic for all outputs Programmable PWM control of all outputs Charge pump output for reverse polarity protection
Rear door actuator driver with bridges for door lock and safe lock and two 5W or 10W - light bulbs.
Description
The L9951 and L9951XP are microcontroller driven, multifunctional rear door actuator drivers for automotive applications. Up to two DC motors and two grounded resistive loads can be driven with three half bridges and two hide side drivers. The integrated standard serial peripheral interface (SPI) controls all operation modes (forward, reverse, brake and high impedance). All diagnostic information is available via the SPI.

Table 1.
Device summary
Order codes Package Tube PowerSO-36 PowerSSO-36 L9951 L9951XP Tape and reel L9951TR L9951XPTR
May 2010
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www.st.com 1
Contents
L9951 / L9951XP
Contents
1 2 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 2.2 2.3 2.4 2.5 2.6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 10 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SPI - electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 Dual power supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Standby - mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Over-voltage and under-voltage detection . . . . . . . . . . . . . . . . . . . . . . . . 20 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 20 Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Over load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PWM input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Programmable softstart function to drive loads with higher inrush current 21
4
Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1 4.2 4.3 4.4 4.5 4.6 4.7 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Serial clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Input data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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L9951 / L9951XP
Contents
4.8
Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5 6
Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1 6.2 6.3 6.4 6.5 ECOPACK(R) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PowerSO-36TM package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PowerSSO-36TM package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PowerSO-36TM packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PowerSSO-36TM packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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List of tables
L9951 / L9951XP
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Overvoltage and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Current monitor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 OUT 1 - OUT 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Delay time from standby to active mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Inputs: CSN, CLK, PWM1/2 and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 EN, CSN timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SPI - Input data and status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SPI - Input data and status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PowerSO-36TM mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PowerSSO-36TM mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SPI - transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI - input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI - DO valid data delay time and valid time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI - DO enable and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI - driver turn-on/off timing, minimum CSN HI time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SPI - timing of status bit 0 (fault condition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Example of programmable softstart function for inductive loads . . . . . . . . . . . . . . . . . . . . 21 Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PowerSO-36TM package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PowerSSO-36TM package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PowerSO-36TM tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PowerSO-36TM tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PowerSSO-36TM tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PowerSSO-36TM tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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Block diagram and pin description
L9951 / L9951XP
1
Block diagram and pin description
Figure 1. Block diagram
Reverse Polarity Protection
10k
VBAT
* Note: Value of capacitor has to be choosen carefully to limit the VS voltage below absolute maximum ratings in case of an unexpected freewheeling condition of inductive loads (e.g. TSD, POR)
100k
*
VREG
100F 100nF
EMC Optimization
VS
CP
VCC
100
Charge Pump
VCC
OUT1
+ 10
100nF
Driver Interface & Diagnostic
OUT2
Lock M Safe Lock
SPI Interface
** 1k ** 1k ** 1k ** 1k **1k
DI DO CLK CSN
OUT3
M Exterior Light
OUT4 OUT5
EN
C
Safety Light
**1k
CM / PWM
MUX
5
GND ** Note: Resistors between C and L9951 are recommended to limit currents
for negative voltage transients at VBAT (e.g. ISO type 1 pulse) + Note: Using a ferrite instead of 10ohm will additionally improve EMC behavior
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Doc ID 14173 Rev 8
L9951 / L9951XP Table 2.
Pin
Block diagram and pin description Pin definitions and functions
Symbol Function Ground . Reference potential. Note: For the capability of driving the full current at the outputs all pins of GND must be externally connected. Power supply voltage (external reverse protection required). For EMI reason a ceramic capacitor as close as possible to GND is recommended. Note: for the capability of driving the full current at the outputs all pins of VS must be externally connected. Half-bridge output 1. The output is built by a high side and a low side switch, which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal reverse diode (bulk-draindiode: high side driver from output to VS, low side driver from GND to output). This output is over-current and open-load protected. Note: for the capability of driving the full current at the outputs all pins of OUT1 must be externally connected. Serial data input. The input requires CMOS logic levels and receives serial data from the microcontroller. The data is a 16bit control word and the least significant bit (LSB, bit 0) is transferred first. Current monitor output/PWM input. Depending on the selected multiplexer bits (bit 9, 10, 11) of Input Data Register this output sources an image of the instant current through the corresponding high side driver with a ratio of 1/10.000. This pin is bidirectional. The microcontroller can overwrite the current monitor signal to provide a PWM input for all outputs. Testmode: If CSN is raised above 7.5V the device will enter the test mode. In test mode this output can be used to measure some internal signals (see Table 18). Chip select not input / Testmode . This input is low active and requires CMOS logic levels. The serial data transfer between L9951 and micro controller is enabled by pulling the input CSN to low level. If an input voltage of more than 7.5V is applied to CSN pin the L9951 will be switched into a test mode. Serial data output . The diagnosis data is available via the SPI and this tristate-output. The output will remain in tristate, if the chip is not selected by the input CSN (CSN = high). Logic supply voltage . For this input a ceramic capacitor as close as possible to GND is recommended. Serial clock input . This input controls the internal shift register of the SPI and requires CMOS logic levels.
1, 18, 19, 36
GND
6, 7, 14, 15, 23, 24, 29, 32
VS
3, 4, 34
OUT1
8
DI
9
CM/PWM
10
CSN
11
DO
12
VCC
13
CLK
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Block diagram and pin description Table 2.
Pin
L9951 / L9951XP
Pin definitions and functions (continued)
Symbol Function Half-bridge output 2 (see OUT1 - pin 3, 4). Note: for the capability of driving the full current at the outputs all pins of OUT2 must be externally connected. Half-bridge output 3 (see OUT1 - pin 3, 4). Note: for the capability of driving the full current at the outputs all pins of OUT3 must be externally connected. Charge Pump Output . This output is provided to drive the gate of an external n-channel power MOS used for reverse polarity protection (see Figure 1). Enable input. If Enable input is forced to GND the device will enter Standby-Mode. The outputs will be switched off and all registers will be cleared
16, 17
OUT2
20, 21
OUT3
26
CP
27
EN
33, 35
High side driver output 4, 5 . The output is built by a high side switch and is intended for resistive loads, hence the internal reverse diode from GND to the output is OUT4, OUT5 missing. For ESD reason a diode to GND is present but the energy which can be dissipated is limited. The high side driver is a power DMOS transistor with an internal reverse diode from the output to VS (bulkdrain-diode). The output is over-current and open-load protected.
Figure 2.
Configuration diagram (top view)
GND N.C. OUT1 OUT1 N.C. VS VS DI CM/PWM CSN DO VCC CLK VS VS OUT2 OUT2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
36 35 34 33 32 31 30 29
GND OUT5 OUT1 OUT4 VS N.C. N.C. N.C. VS . VS. N.C. EN CP N.C. VS VS N.C. OUT3 OUT3 GND
Chip
28 27 26 25 24 23 22 21 20 19
Leadframe
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L9951 / L9951XP
Electrical specifications
2
2.1
Electrical specifications
Absolute maximum ratings
Stressing the device above the rating listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics sure program and other relevant quality document Table 3. Absolute maximum ratings
Symbol VS VCC VDI,VDO,VCLK,VCSN,VEN VCM VCP IOUT1,2,3 IOUT4,5 Parameter DC supply voltage Single pulse tmax < 400ms Stabilized supply voltage, logic supply Digital input / output voltage Current monitor output Charge pump output Output current Output current Value -0.3 to 28 40 -0.3 to 5.5 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -25 to VS + 11 10 5 Unit V V V V V V A A
2.2
ESD protection
Table 4. ESD protection
Parameter All pins Output pins: OUT1 - OUT5
1. HBM according to CDF-AEC-Q100-002. 2. HBM with all unzapped pins grounded.
Value 4(1) 8
(2)
Unit kV kV
2.3
Thermal data
Table 5.
Symbol Tj
Thermal data
Parameter Operating junction temperature Value -40 to 150 Unit C
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Electrical specifications
L9951 / L9951XP
2.4
Temperature warning and thermal shutdown
Table 6.
Symbol TjTW ON TjTW OFF
Temperature warning and thermal shutdown
Parameter Temperature warning threshold junction temperature Temperature warning threshold junction temperature Tj increasing Tj decreasing 130 5 Tj increasing Tj decreasing 150 5 170 Min. Typ. Max. 150 Unit C C K C C K
TjTW HYS Temperature warning hysteresis TjSD ON TjSD OFF Thermal shutdown threshold junction temperature Thermal shutdown threshold junction temperature
TjSD HYS Thermal shutdown hysteresis
2.5
Electrical characteristics
VS = 8 to 16 V, VCC = 4.5 to 5.3 V, Tj = - 40 to 150 C, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. Table 7.
Symbol VS
Supply
Parameter Operating supply voltage range VS DC supply current VS = 13V, VCC = 5.0V active mode OUT1 - OUT5 floating VS = 13V, VCC = 0V standby mode OUT1 - OUT5 floating Ttest =-40C, 25C Ttest = 130C Test condition Min. 7 Typ. Max. 28 Unit V
7
20
mA
IS VS quiescent supply current
3
10
A
6
20
A
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Doc ID 14173 Rev 8
L9951 / L9951XP Table 7.
Symbol
Electrical specifications Supply (continued)
Parameter Test condition VS = 13V, VCC = 5.0V CSN = VCC active mode VS = 13V, VCC = 5.0V CSN = VCC standby mode OUT1 - OUT5 floating VS = 13V, VCC = 5.0V CSN = VCC standby mode OUT1 - OUT5 floating Min. Typ. Max. Unit
VCC DC supply current ICC VCC quiescent supply current
1
3
mA
1
3
A
IS + ICC
Sum quiescent supply current
7
23
A
Table 8.
Symbol
Overvoltage and undervoltage detection
Parameter Test condition VS increasing VS decreasing VSUV ON - VSUV OFF VS increasing VS decreasing VSOV OFF - VSOV ON VCC increasing VCC decreasing VPOR OFF - VPOR ON 3.1 0.3 18 17.5 0.5 4.4 Min. 6.0 5.4 0.55 24.5 Typ. Max. 7.2 6.5 Unit V V V V V V V V V
VSUV ON VS UV-threshold voltage VSUV OFF VS UV-threshold voltage VSUV hyst VS UV-hysteresis VSOV OFF VS OV-threshold voltage VSOV ON VS OV-threshold voltage VSOV hyst VS OV-hysteresis VPOR OFF Power-on-reset threshold VPOR ON Power-on-reset threshold VPOR hyst Power-on-reset hysteresis
Table 9.
Symbol VCM ICM,r
Current monitor output
Parameter Functional voltage range Current monitor output ratio: ICM / IOUT1,2,3,4,5 Test condition VCC = 5V 0V VCM 4V, VCC=5V 0V VCM 4V, VCC=5V, IOUT1-5,low =500mA IOUT1,high =6A IOUT2,3,high =4.9A IOUT4,5,high =1.2A (FS=full scale=600 A) Min. 0 1:10000 Typ. Max. 4 Unit V -
ICM acc
Current monitor accuracy
4% + 1%FS
8% + 2%FS
-
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Electrical specifications Table 10.
Symbol
L9951 / L9951XP
Charge pump output
Parameter Charge pump output voltage Charge pump output current Test condition VS=8V, ICP = -60A Min. 6 8 10 100 150 Typ. Max. 13 13 13 300 Unit V V V A
VCP
VS=10V, ICP = -80A VS12V, ICP = -100A
ICP
VCP = VS+10V VS =13.5V
Table 11.
Symbol
OUT 1 - OUT 5
Parameter Test condition VS = 13.5 V, Tj = 25 C, IOUT1 = 3 A Min. Typ. 150 225 150 200 300 200 800 1250 800 7.4 5.0 1.25 Max. 200 300 200 270 400 270 1100 1700 1100 15.5 10.5 2.6 Unit m m m m m m m m m A A A
RON OUT1
On-resistance to supply or GND
VS = 13.5 V, Tj = 125 C, IOUT1 = 3 A VS = 8.0 V, Tj = 25 C, IOUT1 = 3 A VS = 13.5 V, Tj = 25 C, IOUT2,3 = 3 A
RON OUT2 On-resistance to supply RON OUT3 or GND
VS = 13.5 V, Tj = 125 C, IOUT2,3 = 3 A VS = 8.0 V, Tj = 25 C, IOUT2,3 = 3 A VS = 13.5 V, Tj = 25 C, IOUT4,5 = 0.8 A
rON OUT4, On-resistance to supply rON OUT5 or GND
VS = 13.5 V, Tj = 125 C, IOUT4,5 = 0.8 A VS = 8.0 V, Tj = 25 C, IOUT4,5 = 0.8 A
|IOUT1| |IOUT2|, |IOUT3| |IOUT4|, |IOUT5| td ON H
Output current limitation to supply or GND Output current limitation to supply or GND Output current limitation to GND Output delay time, highside driver on Output delay time, highside driver off Output delay time, lowside driver on
Sink and source Sink and source Source VS = 13.5 V, corresponding lowside driver is not active VS = 13.5 V VS = 13.5 V, corresponding highside driver is not active
20
40
90
s
td OFF H
80
200
300
s
td ON L
20
60
80
s
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L9951 / L9951XP Table 11.
Symbol td OFF L tD HL tD LH
Electrical specifications OUT 1 - OUT 5 (continued)
Parameter Output delay time, lowside driver off Cross current protection time, source to sink Cross current protection time, sink to source Test condition VS = 13.5 V td ON L - td OFF H, td ON H - td OFF L 0 -40 0 -40 70 70 Min. 80 Typ. 150 200 200 -2 -15 50 -15 160 160 Max. 300 400 400 -5 0 100 0 240 240 Unit s s s A A A A mA mA
IQLH
VOUT1-5 = 0V, standby Switched-off output current highside drivers of mode OUT1-5 VOUT1-5 = 0V, active mode Switched-off output current lowside drivers of OUT1-3 Open-load detection current of OUT1 Open-load detection current of OUT2, OUT3 Open-load detection current of OUT4 and OUT5 Minimum duration of open-load condition to set the status bit Minimum duration of over-current condition to switch off the driver VS =13.5 V Iload = 1.5 A VS = 13.5 V Iload = 1.5 A VS = 13.5 V Iload = - 0.8 A VOUT1-3 = VS, standby mode VOUT1-3= VS, active mode
IQLL
IOLD1 IOLD23
IOLD45
5
15
40
mA
tdOL
500
3000
s
tISC
10
100
s
dVOUT1/dt Slew rate of OUT1 dVOUT23/dt Slew rate of OUT2, OUT3 dVOUT45/dt Slew rate of OUT4, OUT5
0.1 0.1 0.1
0.2 0.2 0.2
0.4 0.4 0.4
V/s V/s V/s
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Electrical specifications
L9951 / L9951XP
2.6
SPI - electrical characteristics
(VS = 8 to 16 V, VCC = 4.5 to 5.3 V, Tj = - 40 to 150 C, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin). Table 12.
Symbol
Delay time from standby to active mode
Parameter Test condition Switching from standby to active mode. Time until not Ready Bit goes low. Min. Typ. Max. Unit
tset
Internal startup time
80
300
s
Table 13.
Symbol VinL VinH VinHyst ICSN in ICLK in IDI in IEN in C in
Inputs: CSN, CLK, PWM1/2 and DI
Parameter Input low level Input high level Input hysteresis Pull up current at input CSN Pull down current at input CLK Pull down current at input DI Pull down resistance at input EN Input capacitance at input CLK, DI and PWM VCC = 0 to 5.3V Test condition VCC = 5V VCC = 5V VCC = 5V VCSN = 3.5V VCC = 5V VCLK = 1.5V VDI = 1.5V 0.5 -50 10 10 100 -25 25 25 210 10 -10 50 50 480 15 Min. 1.5 Typ. 2.0 3.0 3.5 Max. Unit V V V A A A k pF
Note:
Value of input capacity is not measured in production test. Parameter guaranteed by design. Table 14.
Symbol tCLK tCLKH tCLKL tset CSN tset CLK tset DI thold time
DI timing(1)
Parameter Clock period Clock high time Clock low time CSN setup time, CSN low before rising edge of CLK CLK setup time, CLK high before rising edge of CSN DI setup time DI hold time Test condition VCC = 5V VCC = 5V VCC = 5V VCC = 5V VCC = 5V VCC = 5V VCC = 5V Min. 1000 400 400 400 400 200 200 Typ. Max. Unit ns ns ns ns ns ns ns
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Doc ID 14173 Rev 8
L9951 / L9951XP Table 14.
Symbol tr in tf in
1.
Electrical specifications DI timing(1) (continued)
Parameter Rise time of input signal DI, CLK, CSN Fall time of input signal DI, CLK, CSN Test condition VCC = 5V VCC = 5V Min. Typ. Max. 100 100 Unit ns ns
See Figure 3 and Figure 4
Note:
DI timing parameters tested in production by a passed/failed test: Tj= -40C/+25C: SPI communication @2MHZ. Tj= +125C: SPI communication @1.25MHZ. Table 15.
Symbol VDOL VDOH IDOLK CDO (1)
DO
Parameter Output low level Output high level Tristate leakage current Tristate input capacitance Test condition VCC = 5 V, ID = -4mA VCC = 5 V, ID = 4 mA VCSN = VCC, 0V < VDO < VCC VCSN = VCC, 0V < VCC < 5.3V VCC -0.4 -10 10 Min. Typ. 0.2 VCC -0.2 10 15 Max. 0.4 Unit V V A pF
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
Table 16.
Symbol tr DO tf DO ten DO tri L tdis DO L tri ten DO tri H tdis DO H tri td DO
DO timing(1)
Parameter DO rise time DO fall time DO enable time from tristate to low level DO disable time from low level to tristate Test condition CL = 100 pF, Iload = -1mA CL = 100 pF, Iload = 1mA CL = 100 pF, Iload = 1mA pull-up load to VCC CL = 100 pF, Iload = 4 mA pull-up load to VCC Min. Typ. 80 50 100 380 100 380 50 Max. 140 100 250 450 250 450 250 Unit ns ns ns ns ns ns ns
DO enable time CL =100 pF, Iload = -1mA from tristate to high level pull-down load to GND DO disable time CL = 100 pF, Iload = -4mA from high level to tristate pull-down load to GND DO delay time VDO < 0.3 VCC, VDO > 0.7VCC, CL = 100pF
1. See Figure 5 and Figure 6.
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Electrical specifications Table 17.
Symbol
L9951 / L9951XP
EN, CSN timing(1)
Parameter Test condition Transfer of SPI-command to input register Transfer of SPI-command to input register Min. Typ. 20 Max. 50 Unit s
Minimum EN high before tEN_CSN_LO sending first SPI frame, i.e. CSN going low tCSN_HI,min Minimum CSN HI time between two SPI frames
2
4
s
1. See Figure 7
Figure 3.
CSN
SPI - transfer timing diagram
CSN high to low: DO enabled
time
CLK
0
1
2
3
4
5
6
7
8
9
10 11 12
13 14 15
0
1
time
DI: data will be accepted on the rising edge of CLK signal actual data
new data
10 11 12 13 14 15 0 1
time
DI
0
1
2
3
4
5
6
7
8
9
DO: data will change on the falling edge of CLK signal status information
DO
0
1
2
3
4
5
6
7
8
9
10 11 12
13 14 15
0
1
time
fault bit
CSN low to high: actual data is transfered to output power switches old data actual data
e.g.OUT1
time
Figure 4.
SPI - input timing
0.8 VCC 0.2 VCC t set CSN t CLKH t set CLK 0.8 VCC 0.2 VCC t set DI t hold DI t CLKL 0.8 VCC
CSN
CLK
DI
Valid
Valid 0.2 VCC
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Doc ID 14173 Rev 8
L9951 / L9951XP Figure 5. SPI - DO valid data delay time and valid time
t f in t r in
Electrical specifications
CLK t r DO DO (low to high) t d DO DO (high to low) t f DO
0.8 VCC 0.5 VCC 0.2 VCC
0.8 VCC 0.2 VCC
0.8 VCC 0.2 VCC
Figure 6.
SPI - DO enable and disable time
tf in tr in
CSN
0.8 VCC 50% 0.2 VCC
DO pull-up load to VCC CL = 100 pF
50%
ten DO tri L t dis DO L tri
DO pull-down load to GND CL = 100 pF ten DO tri H t dis DO H tri
50%
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Electrical specifications Figure 7. SPI - driver turn-on/off timing, minimum CSN HI time
CSN low to high: data from shift register is transferred to output power switches
L9951 / L9951XP
t r in
tCSN_HI,min
t f in
80%
CSN 50% 20%
tdOFF output current of a driver
80% 50% 20%
ON state
OFF state
t OFF tdON t ON output current of a driver 80% 50% 20%
OFF state
ON state
Figure 8.
SPI - timing of status bit 0 (fault condition)
CSN high to low and CLK stays low: status information of data bit 0 (fault condition) is transfered to DO
CSN time CLK time DI time
DI: data is not accepted
DO
0 time
DO: status information of data bit 0 (fault condition) will stay as long as CSN is low
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L9951 / L9951XP
Application information
3
3.1
Application information
Dual power supply: VS and VCC
The power supply voltage VS supplies the half bridges and the high side drivers. An internal charge-pump is used to drive the high side switches. The logic supply voltage VCC (stabilized 5V) is used for the logic part and the SPI of the device. Due to the independent logic supply voltage the control and status information will not be lost, if there are temporary spikes or glitches on the power supply voltage. In case of power-on (VCC increases from under voltage to VPOR OFF = 4.0V, typical) the circuit is initialized by an internally generated power-on-reset (POR). If the voltage VCC decreases under the minimum threshold (VPOR ON =3.6V, typical), the outputs are switched to tristate (high impedance) and the status registers are cleared.
3.2
Standby - mode
The standby mode of the L9951 is activated by switching the EN input do GND. All latched data will be cleared and the inputs and outputs are switched to high impedance. In the standby mode the current at VS (VCC) is less than 3 A (1A) for CSN = high (DO in tristate). If EN is switched to 5V the device will enter the active mode. In the active mode the chargepump and the supervisor functions are activated.
3.3
Inductive loads
Each half bridge is built by an internally connected high side and a low side power DMOS transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs OUT1 to OUT3 without external free-wheeling diodes. The high side drivers OUT4 to OUT5 are intended to drive resistive loads. Hence only a limited energy (E<0.5mJ) can be dissipated by the internal ESD-diodes in freewheeling condition. For inductive loads (L > 50H) an external free-wheeling diode connected to GND and the corresponding output is needed.
3.4
Diagnostic functions
All diagnostic functions (over/open-load, power supply over-/undervoltage, temperature warning and thermal shutdown) are internally filtered and the condition has to be valid for at least 32s (open-load: 1ms, respectively) before the corresponding status bit in the status registers will be set. The filters are used to improve the noise immunity of the device. Openload and temperature warning function are intended for information purpose and will not change the state of the output drivers. On contrary, the over load and thermal shutdown condition will disable the corresponding driver (over load) or all drivers (thermal shutdown), respectively. Without setting the over-current recovery bit in the Input Data Register to logic high, the microcontroller has to clear the over-current status bit to reactivate the corresponding driver. Each driver has a corresponding over-current recovery bit. If this bit is set, the device will automatically switch-on the outputs again after a short recovery time. The duty cycle in over-current condition can be programmed by the SPI interface (12% or 25%). With this feature the device can drive loads with start-up currents higher than the overcurrent limits (e.g. inrush current of lamps, cold resistance of motors and heaters).
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Application information
L9951 / L9951XP
3.5
Over-voltage and under-voltage detection
If the power supply voltage VS rises above the over-voltage threshold VSOV OFF (typical 21V), the outputs OUT1 to OUT5 are switched to high impedance state to protect the load and the internal charge-pump is turned-off. When the voltage VS drops below the undervoltage threshold VSUV OFF (UV-switch-OFF voltage), the output stages are switched to the high impedance to avoid the operation of the power devices without sufficient gate driving voltage (increased power dissipation). If the supply voltage VS recovers to normal operating voltage the output stages return to the programmed state (input register 0: bit 12=0). If the undervoltage / overvoltage recovery disable bit is set, the automatic turn-on of the drivers is deactivated. The microcontroller needs to clear the status bits to reactivate the drivers.
3.6
Temperature warning and thermal shutdown
If junction temperature rises above Tj TW a temperature warning flag is set and is detectable via the SPI. If junction temperature increases above the second threshold Tj SD, the thermal shutdown bit will be set and power DMOS transistors of all output stages are switched off to protect the device. In order to reactivate the output stages the junction temperature must decrease below TjSD - TjSD HYS and the thermal shutdown bit has to be cleared by the microcontroller.
3.7
Open-load detection
The open-load detection monitors the load current in each activated output stage. If the load current is below the open-load detection threshold for at least 1 ms (tdOL) the corresponding open-load bit is set in the status register. Due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3ms) can be used to test the open-load status without changing the mechanical/electrical state of the loads.
3.8
Over load detection
In case of an over-current condition a flag is set in the status register in the same way as open-load detection. If the over-current signal is valid for at least tISC=32s, the over-current flag is set and the corresponding driver is switched off to reduce the power dissipation and to protect the integrated circuit. If the over-current recovery bit of the output is zero the microcontroller has to clear the status bits to reactivate the corresponding driver.
3.9
Current monitor
The current monitor output sources a current image at the current monitor output which has a fixed ratio (1/10000) of the instantaneous current of the selected high side driver. The bits 9, 10 and 11 of the input data register 0 control which of the outputs OUT1 to OUT5 will be multiplexed to the current monitor output. The current monitor output allows a more precise analysis of the actual state of the load rather than the detection of an open- or overload condition. For example this can be used to detect the motor state (starting, free-running, stalled). Moreover, it is possible to regulate the power of the defroster more precise by measuring the monitor current.
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L9951 / L9951XP
Application information
3.10
PWM input
Each driver has a corresponding PWM enable bit which can be programmed by the SPI interface. If the PWM enable bit is set, the outputs OUT1 to OUT5 are controlled by the logically AND-combination of the signal applied to the PWM input and the output control bit in input data register1.
3.11
Cross-current protection
The three half-brides of the device are cross-current protected by an internal delay time. If one driver (LS or HS) is turned-off the activation of the other driver of the same half bridge will be automatically delayed by the cross-current protection time. After the cross-current protection time is expired the slew-rate limited switch-off phase of the driver will be changed to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. Due to this behavior it is always guaranteed that the previously activated driver is totally turned-off before the opposite driver will start to conduct.
3.12
Programmable softstart function to drive loads with higher inrush current
Loads with start-up currents higher than the over-current limits (e.g. inrush current of lamps, start current of motors and cold resistance of heaters) can be driven by using the programmable softstart function (i.e. overcurrent recovery mode). Each driver has a corresponding over-current recovery bit. If this bit is set, the device will automatically switchon the outputs again after a programmable recovery time. The duty cycle in over-current condition can be programmed by the SPI interface to be about 12% or 25%. The PWM modulated current will provide sufficient average current to power up the load (e.g. heat up the bulb) until the load reaches operating condition. The device itself cannot distinguish between a real overload and a non linear load like a light bulb. A real overload condition can only be qualified by time. As an example the microcontroller can switch on light bulbs by setting the over-current Recovery bit for the first 50ms. After clearing the recovery bit the output will be automatically disabled if the overload condition still exits. Figure 9. Example of programmable softstart function for inductive loads
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Functional description of the SPI
L9951 / L9951XP
4
4.1
Functional description of the SPI
Serial Peripheral Interface (SPI)
This device uses a standard SPI to communicate with a microcontroller. The SPI can be driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0 and CPHA = 0. For this mode, input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK. This device is not limited to microcontroller with a build-in SPI. Only three CMOS-compatible output pins and one input pin will be needed to communicate with the device. A fault condition can be detected by setting CSN to low. If CSN = 0, the DO-pin will reflect the status bit 0 (fault condition) of the device which is a logical-or of all bits in the status registers 0 and 1. The microcontroller can poll the status of the device without the need of a full SPIcommunication cycle.
Note:
In contrast to the SPI-standard the least significant bit (LSB) will be transferred first (see Figure 3).
4.2
Chip Select Not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the output pin (DO) will be in high impedance state. A low signal will activate the output driver and a serial communication can be started. The state when CSN is going low until the rising edge of CSN will be called a communication frame. If the CSN-input pin is driven above 7.5V, the L9951 will go into a test mode. In the test mode the DO will go from tristate to active mode.
4.3
Serial Data In (DI)
The input pin is used to transfer data serial into the device. The data applied to the DI will be sampled at the rising edge of the CLK signal and shifted into an internal 16 bit shift register. At the rising edge of the CSN signal the contents of the shift register will be transferred to Data Input Register. The writing to the selected Data Input Register is only enabled if exactly 16 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame will be ignored. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame.
Note:
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended.
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L9951 / L9951XP
Functional description of the SPI
4.4
Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go from high impedance to a low or high level depending on the status bit 0 (fault condition). The first rising edge of the CLK input after a high to low transition of the CSN pin will transfer the content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK will shift the next bit out.
4.5
Serial clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input (DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the falling edge of the CLK signal.
4.6
Input data register
The device has two input registers. The first bit (bit 0) at the DI-input is used to select one of the two input registers. All bits are first shifted into an input shift register. After the rising edge of CSN the contents of the input shift register will be written to the selected input data register only if a frame of exact 16 data bits are detected. Depending on bit 0 the contents of the selected status register will be transferred to DO during the current communication frame. Bit 1-8 control the behavior of the corresponding driver. The bits 9,10 and 11 are used to control the current monitor multiplexer. Bit 15 is used to reset all status bits in both status registers. The bits in the status registers will be cleared after the current communication frame (rising edge of CSN).
4.7
Status register
This devices uses two status registers to store and to monitor the state of the device. Bit 0 is used as a fault bit and is a logical-NOR combination of bits 1-14 in both status registers. The state of this bit can be polled by the microcontroller without the need of a full SPIcommunication cycle (see Figure 8.). If one of the over-current bits is set, the corresponding driver will be disabled. If the over-current recovery bit of the output is not set the microcontroller has to clear the over-current bit to enable the driver. If the thermal shutdown bit is set, all drivers will go into a high impedance state. Again the microcontroller has to clear the bit to enable the drivers.
4.8
Test mode
The test mode can be entered by rising the CSN input to a voltage higher than 7.5V. In the test mode the inputs CLK, DI, PWM and the internal 2MHz CLK can be multiplexed to data output DO for testing purpose. Furthermore the over-current thresholds are reduced by a factor of 4 to allow EWS testing at lower current. The internal logic prevents that the Hi-Side and Low-Side driver of the same half-bridge can be switched-on at the same time. In the test mode this combination is used to multiplex the desired signals to the CM output according to table 18 and 19.
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Functional description of the SPI Table 18.
LS1 HS1 ! (both HI) both HI ! (both HI) both HI ! (both HI)
L9951 / L9951XP
Test mode
LS2 HS2 ! (both HI) ! (both HI) both HI both HI ! (both HI) LS3 HS3 ! (both HI) ! (both HI) ! (both HI) ! (both HI) both HI DO NoError DI CLK INT_CLK PWM LS1 HS1 ! (both HI) both HI ! (both HI) both HI ! (both HI) both HI ! (both HI) both HI LS2 HS2 ! (both HI) ! (both HI) both HI both HI ! (both HI) ! (both HI) both HI both HI LS3 HS3 ! (both HI) ! (both HI) ! (both HI) ! (both HI) both HI both HI both HI both HI CM N.C Tsense1 Tsense2 Tsense3 Tsense4 N.C 5A Iref Vbandgap
Table 19.
SPI - Input data and status register 0
Input register 0 (write) Status register 0 (read) Name Comment A broken VCC-or SPIconnection of the L9951 can be detected by the microcontroller, because all 16 bits low or high is not a valid frame.
Bit
Name
Comment
15
Reset bit
If reset bit is set both status registers will be cleared after rising edge of CSN input.
Always 1
14
Disable openload
If the disable open-load bit is set, the open-load status bits will be ignored for the NonErrorBit calculation.
In case of an over-voltage or VS undervoltage event the over-voltage corresponding bit is set and the outputs are deactivated.
13
This bit defines in combination with the overcurrent recovery bit (input register 1) the duty cycle in over-current condition of an activated driver. If temperature warning bit is 0: 12% 1: 25% set, L9951 will always use the lower duty cycle OC recovery duty cycle Overvoltage/ under-voltage recovery disable If this bit is set the microcontroller has to clear the status register after undervoltage/overvoltage event to enable the outputs.
If VS voltage recovers to normal operating conditions VS undervoltage outputs are reactivated automatically.
12
Thermal shutdown
In case of an thermal shutdown all outputs are switched off. The microcontroller has to clear the TSD bit by setting the reset bit to reactivate the outputs.
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L9951 / L9951XP Table 19.
Functional description of the SPI SPI - Input data and status register 0 (continued)
Input register 0 (write) Status register 0 (read) Name Comment
Bit
Name
Comment Following current image (1/10.000) of the HS driver will be multiplexed to CM output:
11
This bit is for information purpose only. It can be used Temperature for a thermal management by warning the microcontroller to avoid a thermal shutdown. After switching the device from standby mode to active mode an internal timer is started to allow charge pump to settle before the outputs can be activated. This bit is cleared Not ready bit automatically after start up time has finished. Since this bit is controlled by internal clock it can be used for synchronizing testing events (e.g. measuring filter times). 0 Not used
Current monitor select bits 10
Bit 11 Bit 10 Bit 9 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0
Output OUT1 OUT2 OUT3 OUT4 OUT5
9 8 7 6 5 4 3 2 1 OUT5 - HS on/off OUT4 - HS on/off OUT3 - HS on/off OUT3 - LS on/off OUT2 - HS on/off OUT2 - LS on/off OUT1 - HS on/off OUT1 - LS on/off If a bit is set the selected output driver is switched on. If the corresponding PWM enable bit is set (Input Register 1) the driver is only activated if PWM input signal is high. The outputs of OUT1-OUT3 are half bridges. If the bits of HSand LS-driver of the same half bridge are set, the internal logic prevents that both drivers of this output stage can be switched on simultaneously in order to avoid a high internal current from VS to GND.
OUT5-HS over - current OUT4-HS In case of an over-current over - current event the corresponding status bit is set and the output driver OUT3-HS is disabled. If the over-current over - current recovery enable bit is set (Input Register 1) the output OUT3-LS will be automatically over - current reactivated after a delay time OUT2-HS resulting in a PWM modulated current with a programmable over - current duty cycle (Bit 13). OUT2-LS If the over-current recovery bit over - current is not set the microcontroller has to clear the over-current bit OUT1-HS (reset bit) to reactivate the over - current output driver. OUT1-LS over - current A logical NOR-combination of all bits 1 to 14 in both status registers. If bit 14 (disable open-load) is set, the openload status will be ignored.
0
0
No error bit
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Functional description of the SPI Table 20. SPI - Input data and status register 1
Input register 1 (write) Bit Name Comment Name
L9951 / L9951XP
Status register 1 (read) Comment A broken VCC-or SPIconnection of the L9951 can be detected by the microcontroller, because all 16 bits low or high is not a valid frame.
15
Not used
Always 1
14
Not used
In case of an over-voltage or undervoltage event the VS over-voltage corresponding bit is set and the outputs are deactivated. In case of an over-voltage or undervoltage event the VS undervoltage corresponding bit is set and the outputs are deactivated. In case of an thermal shutdown all outputs are switched off. The microcontroller has to clear the TSD bit by setting the reset bit to reactivate the outputs. This bit is for information purpose only. It can be used for a thermal management by the microcontroller to avoid a thermal shutdown.
13
Not used
12
Not used
Thermal shutdown
11
Not used
Temperature warning
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L9951 / L9951XP Table 20.
Functional description of the SPI SPI - Input data and status register 1 (continued)
Input register 1 (write) Status register 1 (read) Name Comment After switching the device from standby mode to active mode an internal timer is started to allow charge pump to settle before the outputs can be activated. This bit is cleared automatically after start up time has finished. Since this bit is controlled by internal clock it can be used for synchronizing testing events(e.g. measuring filter times). Not used.
Bit
Name
Comment
10
9 8 7
In case of an over-current event the over-current status bit (status register 0) is set and the output is switched off. If the overcurrent recovery enable bit OUT5 OC is set the output will be recovery enable automatically reactivated after a delay time resulting in a PWM modulated current with a programmable duty cycle (Bit 13 of Input data register 1). OUT4 OC recovery enable OUT3 OC Depending on occurrence recovery enable of overcurrent event and internal clock phase it is OUT2 OC recovery enable possible that one recovery cycle is executed even if this bit is set to zero. OUT1 OC recovery enable OUT5 PWM enable OUT4 PWM enable OUT3 PWM enable OUT2 PWM enable OUT1 PWM enable If the PWM enable bit is set and the output is enabled (input register 0) the output is switched on if PWM input is high and switched off if PWM input is low.
Not ready bit
0 OUT5-HS open-load OUT4-HS open-load OUT3-HS open-load OUT3-LS open-load OUT2-HS open-load OUT2-LS open-load OUT1-HS open-load OUT1-LS open-load
6
5 4 3 2 1
The open-load detection monitors the load current in each activated output stage. If the load current is below the open-load detection threshold for at least 1 ms (tdOL) the corresponding open-load bit is set. Due to mechanical /electrical inertia of typical loads a short activation of the outputs (e.g. 3ms) can be used to test the open-load status without changing the mechanical/electrical state of the loads.
0
1
No error bit
A logical NOR-combination of all bits 1 to 14 in both status registers. If bit 14 (Disable Open-Load) is set, the openload status will be ignored
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Packages thermal data
L9951 / L9951XP
5
Packages thermal data
Figure 10. Packages thermal data
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Doc ID 14173 Rev 8
L9951 / L9951XP
Package and packing information
6
6.1
Package and packing information
ECOPACK(R) packages
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark.
6.2
PowerSO-36TM package information
Figure 11. PowerSO-36TM package dimensions
Table 21.
PowerSO-36TM mechanical data
Millimeters
Symbol Min. A a1 a2 a3 b c 0 0.22 0.23 0.10 Typ. Max. 3.60 0.30 3.30 0.10 0.38 0.32
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Package and packing information Table 21. PowerSO-36TM mechanical data (continued)
Millimeters Symbol Min. D* D1 E E1 * E2 E3 e e3 G H h L M N R s 0.8 0 15.50 5.80 0.65 11.05 15.80 9.40 13.90 10.90 Typ.
L9951 / L9951XP
Max. 16.00 9.80 14.5 11.10 2.90 6.20
0.10 15.90 1.10 1.10
10 deg
8 deg
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L9951 / L9951XP
Package and packing information
6.3
PowerSSO-36TM package information
Figure 12. PowerSSO-36TM package dimensions
Table 22.
PowerSSO-36TM mechanical data
Millimeters Min. 2.15 0 0.18 0.23 10.10 7.4 Typ. 0.5 8.5 2.3 10.1 0 0.55 0.1 0.06 10.5 0.4 8 0.85 10 deg Max. 2.45 2.35 0.1 0.36 0.32 10.50 7.6 -
Symbol A A2 a1 b c D* E* e e3 F G G1 H h k L N
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Package and packing information Table 22. PowerSSO-36TM mechanical data (continued)
Millimeters Min. 4.3 6.9 Typ. -
L9951 / L9951XP
Symbol X Y
Max. 5.2 7.5
6.4
PowerSO-36TM packing information
Figure 13. PowerSO-36TM tube shipment (no suffix)
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L9951 / L9951XP
Package and packing information
Figure 14. PowerSO-36TM tape and reel shipment (suffix "TR")
TAPE DIMENSIONS A0 B0 K0 K1 F P1 W 15.20 0.1 16.60 0.1 3.90 0.1 3.50 0.1 11.50 0.1 24.00 0.1 24.00 0.3
REEL DIMENSIONS
Base Qty Bulk Qty A (max) B (min) C (0.2) D (min) G (+2 / -0) N (min) T (max) 600 600 330 1.5 13 20.2 24.4 60 30.4
All dimensions are in mm.
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Package and packing information
L9951 / L9951XP
6.5
PowerSSO-36TM packing information
Figure 15. PowerSSO-36TM tube shipment (no suffix)
Base Qty Bulk Qty Tube length (0.5) A B C (0.1) All dimensions are in mm.
A
C
B
49 1225 532 3.5 13.8 0.6
Figure 16. PowerSSO-36TM tape and reel shipment (suffix "TR")
REEL DIMENSIONS
Base Qty Bulk Qty A (max) B (min) C (0.2) F G (+2 / -0) N (min) T (max) TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing All dimensions are in mm. W P0 (0.1) P D (0.05) D1 (min) F (0.1) K (max) P1 (0.1) 24 4 12 1.55 1.5 11.5 2.85 2
1000 1000 330 1.5 13 20.2 24.4 100 30.4
End
Start Top cover tape No components Components 500mm min No components
500mm min Empty components pockets sealed with cover tape. User direction of feed
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Doc ID 14173 Rev 8
L9951 / L9951XP
Revision history
7
Revision history
Table 23.
Date Mar-2004 Jun-2005 Jul-2005 Sep-2005 Feb-2006 15-Nov-2007
Document revision history
Revision 1 2 3 4 5 6 First issue Added PowerSO-36TM package information, PowerSO-36TM package information. Updated Figure 1.: Block diagram . Note 1 removal; Updated Figure 10.: Packages thermal data. Updated Table 4.: ESD protection. Document restructured and reformatted. Added PowerSO-36TM packing information and PowerSSO-36TM packing information. Table 22: PowerSSO-36TM mechanical data: - Deleted A (min) value - Changed A (max) value from 2.47 to 2.45 - Changed A2 (max) value from 2.40 to 2.35 - Changed a1 (max) value from 0.075 to 0.1 - Added F and k rows Table 22: PowerSSO-36TM mechanical data: - Changed X: minimum value from 4.1 to 4.3 and maximum value from 4.7 to 5.2 - Changed Y: minimum value from 6.5 to 6.9 and maximum value from 7.1 to 7.5 Description of changes
24-Jun-2009
7
14-May-2010
8
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L9951 / L9951XP
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Doc ID 14173 Rev 8

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